Info

ASC is developing cutting-edge EDA solutions, which will empower the chip designers, for the first time, to optimize power simultaneously with area and speed at the early stages of the chip design. ASC's approach rests on the analysis of the multiple sources of power dissipation on a chip (Figure 1) and development of domain-specific techniques for high-level power optimization. Initial R&D and tool development was performed by ASC under several SBIR contracts from US Air Force and NASA. Princeton University is ASC's technical partner.